The present invention relates to a semiconductor integrated device, which is embedded with a reference potential generation circuit that uses a pseudo memory cell formed on a semiconductor substrate.
With the advancement of semiconductor mounting techniques, inexpensive one-chip microprocessors which have a memory, such as a ROM and the like built in have become available, and have been installed in electronic apparatuses such as clocks, game machines, mobile phones and the like.
A reading circuit for the above-mentioned built-in memory is made of a sense amplifier, and is constituted of a load circuit, a pseudo memory cell (dummy cell) and a transistor, which are arranged at the periphery of a memory cell. Further, these load circuit, dummy cell, and transistor are used to provide a reference voltage to a reading bit line. Moreover, the dummy cell has the same structure as the cell that constitutes the memory.
The basic structure and operation of the reference potential generation circuit in the reading circuit of the above-described built-in memory is, for example, disclosed in Japanese Unexamined Patent Application Publication No. 5-189982.
However, according to the above-mentioned structure, a DC current flows between the load circuit and the dummy cell even during low speed operation of the memory, and the current drain (consumption) generated at that time can no longer be ignored. This phenomenon shows up noticeably in particular when a flash-memory is used as the memory, thus power efficiency has been the most important design problem.
The present invention is made in view of the above-mentioned reasons, and it is an object of the present invention to provide a semiconductor integrated device which aims to reduce current drain (consumption) during low speed operation of a memory by activating a reference potential generation circuit, using a differentiating circuit that generates a short signal when the pulse width of an input signal is long, and also to provide an electronic apparatus into which the device is loaded.
It is also an object of the present invention to provide a semiconductor integrated device in which unstable operation during high speed operation of a memory is prevented by using a clock that is generated through an oscillator when the pulse width of an input signal is short, and by using the above-mentioned differentiating circuit when the pulse width of an input signal is long, and also to provide an electronic apparatus into which the device is loaded.
In order to achieve the above-mentioned object, a semiconductor integrated device of the present invention is such that in a semiconductor integrated device which is embedded with a reference potential generation circuit that uses a memory cell, the semiconductor integrated device includes a differentiating pulse generation circuit for generating a shorter signal when the pulse width of an input signal is long and for activating the reference potential generation circuit.
Also in a semiconductor integrated device which is embedded with a reference potential generation circuit that uses a pseudo memory cell, the semiconductor integrated device is characterized in that with a differentiating pulse generation circuit constituted of a delay circuit and a gate circuit, a shorter signal is generated when the pulse width of an input signal is long, and the reference potential generation circuit is activated.
The above-mentioned semiconductor integrated device is, characterized in that the pseudo memory cell is constituted of a non-volatile memory.
According to the above-mentioned configuration of the present invention, since the time for operating the reference potential generation circuit can be made constant when the operation frequency is low, the duty ratio when the frequency decreases can be made larger, and it is possible to substantially reduce the current consumption.
A second semiconductor integrated device of the present invention is such that in a semiconductor integrated device which is embedded with a reference potential generation circuit that uses a pseudo memory cell, and a sense amplifier that operates by inputting a reference potential that is generated by the reference potential generation circuit, the semiconductor integrated device is characterized in that a reference potential is supplied to the sense amplifier only when a reference potential generation circuit enable signal that is generated by a differentiating pulse generation circuit is active.
Also, in the above-mentioned semiconductor integrated device, the pseudo memory cell is constituted of a non-volatile memory.
According to the above-mentioned configuration of the present invention, since the time for supplying the reference potential to the sense amplifier can be made constant when the operation frequency is low, even when the DC current flows because of insufficient writing of the memory cell, the active time of the sense amplifier can be shortened when the frequency decreases can be made larger, and it is possible to reduce the current consumption.
Also, the above-mentioned semiconductor integrated device is characterized in that a reference potential is supplied to the sense amplifier by the differentiating circuit output when the pulse width of the input signal is long, and by a clock that is generated through an oscillator when the pulse width of the input signal is short-.
Further, in the above-mentioned semiconductor integrated device, a relative length of the pulse width of the input signal is determined by a clock switching signal that is set as programmable in a register which is stored in the device.
Also, in the above-mentioned semiconductor integrated device, a relative length of the pulse width of the input signal is determined by a selection signal of an oscillator that is set as programmable in a register which is stored in the device.
According to the above-mentioned configuration of the present invention, an unstable operation during high speed operation can be prevented by using the above-mentioned differentiating circuit output when the pulse width of the input signal is long, and by using the clock that is generated through the oscillator when the pulse width of the input signal is short. It is possible to reduce the current consumption during low speed operation, and it can be operated at a high frequency in synchronization with the clock during high speed operation.
An electronic apparatus into which a semiconductor integrated device is installed is characterized in that, in the electronic apparatus, the semiconductor integrated device is embedded with a reference potential generation circuit that uses a memory cell, the electronic apparatus being characterized in that the electronic apparatus is installed with the semiconductor integrated device including a differentiating pulse generation circuit for generating a short signal when the pulse width of an input signal is long and for activating the reference potential generation circuit.
Also, the above-mentioned electronic apparatus is installed with a semiconductor integrated device which supplies a reference potential to the sense amplifier by the differentiating circuit output when the pulse width of the input signal is long, and by a clock that is generated through an oscillator when the pulse width of the input signal is short.
According to the above-mentioned configuration, by using the semiconductor integrated device which, with the differentiating circuit, generates a shorter signal when the pulse width of the input signal is long, and activates the reference potential generation circuit, since the duty ratio when the frequency decreases can be made larger, it is possible to provide an electronic apparatus which reduces the current consumption substantially. Further, by using the differentiating circuit when the pulse width of the input signal is long, and by using the clock that is generated through the oscillator when the pulse width of the input signal is short, a reduction of the current consumption is made possible during low speed operation, and thus it is possible to provide an electronic apparatus which operates at a high frequency in synchronization with the clock during high speed operation.